1. Field of the Invention
The present invention relates generally to testing of integrated circuits, and more specifically to a method and apparatus for calculating a number of transitions and estimating the amount of power that would be dissipated in sequential scan tests.
2. Related Art
Sequential scan techniques are often used to test integrated circuits. According to a typical sequential scan technique, integrated circuits are designed to operate in functional mode or test mode. In functional mode, elements in the integrated circuit are connected according to a desired design and to provide a desired utility for which the integrated circuit is primarily designed.
In test mode, the integrated circuit is designed to connect various memory elements (contained in the integrated circuit) such as flip-flops in a sequence referred to as a “scan chain” (i.e., the output of one element is connected as an input to the next element). The first element in the scan chain is generally designed to receive the input bits and the last element of the scan chain is designed to scan out the results of evaluation, as described below.
In a typical scan test scenario, a number of bits in a particular pattern of zeros and ones (input vector) are sequentially (one bit at every clock cycle) loaded (scanned in) into scan chain through the first element. The number of bits contained in the input vector generally equals the number of memory elements in a corresponding scan chain.
Once a scan chain is loaded with a input vector, the elements (generally the combinatorial logic) in the integrated circuit are evaluated based on the scanned in bits. The flip-flops are designed to latch the results of the evaluation, and the bits latched in the scan chain are sequentially scanned out (one bit at every clock cycle) through the last element in the scan chain. The received scan out is compared with an expected scan out corresponding to the input vector to determine the various faults within the integrated circuit.
Many such scan chains are used to extensively test integrated circuits. The number of scan chains, as well as the lengths of the scan chains is typically larger for correspondingly complex/large designs. Each scan chain may in turn be tested with a number of input vectors. Thus, integrated circuits may be tested with a desired set of input vectors to determine whether the integrated circuits operate in a desired manner.
There is often a need to compute the number of transitions (in input and/or output of scan elements) that would occur during such sequential scan tests. For example, such numbers could be used in estimating the power that would be dissipated by integrated circuits during sequential scan tests. The estimate may be relevant, for example, because power dissipated during scan tests is often greater (since many more flip-flops would toggle) than power dissipated during normal operation (non-test duration), and the test power can potentially burn-out portions of the integrated circuit being tested.
Accordingly, the test power for each possible design of an integrated circuit is estimated, and either design or input vectors are changed to ensure that the eventual integrated circuits would operate within the power specifications during sequential scan tests. At least for such a reason, there is a need for estimation of power dissipation for a given set of input vectors.